Full-rate transmitter
US10257121B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2017 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Nov 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03885
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments include systems and methods for transmitting data over high-speed data channels in context of serializer/deserializer circuits. Some embodiments include a novel full-rate source-series-terminated (SST) transmitter driver architecture with output charge sharing isolation. Certain implementations have a programmable floating tap (e.g., in addition to standard taps) with both positive and negative FIR values and cursor reduction, which can help achieve large FIR range and high channel equalization capability. Some embodiments operate with multi-phase clocking having phased clock error correction, which can facilitate operation with low-jitter and low-DCD clocks. Some implementations also include novel output inductor structures that are disposed to partially overlap output interface bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.