Test circuit capable of measuring PLL clock signal in ATPG mode
US10261128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Mar 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed herein is a test circuit for a device under test. The test circuit includes a scan chain configured to receive test pattern data and to shift the test pattern data to the device under test, and being clocked by a reference clock, and a clock circuit configured to operate in either a clock generation mode or a frequency determination mode. The clock circuit, when in the clock generation mode and when the test circuit is in a normal mode of operation, is configured to pass a first clock signal to the device under test. The clock circuit, when in the clock generation mode and when the test circuit is in a test mode of operation, is configured to pass the reference clock to the device under test. The clock circuit, when in the frequency determination mode, counts a frequency of the first clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.