Low dropout regulator (LDO) circuit
US10261533B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 22, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Nov 22, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/618
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
The present disclosure relates to semiconductors and low dropout regulator (LDO) circuits. A LDO circuit may include first and second adjustment pipes and first and second error amplifiers. When an output voltage outputted by the output end of the LDO circuit is smaller than a reference voltage, the first error amplifier controls the first adjustment pipe to be turned on, and the second error amplifier controls the second adjustment pipe to be turned off. Alternative, when the output voltage is greater than the reference voltage, the first error amplifier controls the first adjustment pipe to be turned off, and the second error amplifier controls the second adjustment pipe to be turned on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.