Separate clock synchronous architecture
US10261539B2 · kind B2 · utility
1Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Mar 31, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Jul 22, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a plurality of independently clocked devices and a low frequency beacon. Each of the plurality of independently clocked devices has a respective local clock generator. The low frequency beacon communicates a low frequency synchronization signal to each of the independently clocked devices. The respective local clock generators of the plurality of independently clocked devices are generally synchronized using the low frequency synchronization signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.