Method for wear leveling in a nonvolatile memory
US10261702B2 · kind B2 · utility
2Cited by
8References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 1, 2015 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Jul 14, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for writing and reading data in memory cells, comprising, when writing a data in a block of a first memory zone, a step consisting of writing in a second memory zone a temporary information structure metadata comprising a start flag, an identifier of the temporary information structure, an information about the location of the block in the first memory zone, and a final flag, and, after a power on of the first memory zone, searching for an anomaly in temporary information structures present in the second memory zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.