Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory
US10261901B2 · kind B2 · utility
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35References
17Claims
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Key dates
| Filing date | Sep 25, 2015 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Oct 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is described. The apparatus includes a last level cache and a memory controller to interface to a multi-level system memory. The multi-level system memory has a caching level. The apparatus includes a first prediction unit to predict unneeded blocks in the last level cache. The apparatus includes a second prediction unit to predict unneeded blocks in the caching level of the multi-level system memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.