Accessing cache with access delay reduction mechanism
US10261905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2016 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Jul 20, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for accessing a cache including reading an access instruction for acquiring data; determining, according to a delay identifier carried by the access instruction, whether the access instruction produces a delay; accessing the cache and performing, according to a location identifier carried by the access instruction, a pre-fetch operation if a delay is produced; and modifying, according to a location where the data required by the access instruction is acquired, the delay identifier and the location identifier carried by the access instruction. The technical solutions solve the problem of a low hit rate upon cache access, reduce the probability of misses, and reduce an access delay caused by a level-by-level access to each level of cache upon target data acquisition, which correspondingly lowers the power consumption generated upon the cache access and improves the CPU performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.