Semaphore for multi-core processor
US10261926B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2016 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Jun 10, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-core processor manages contention amongst its cores for access to a shared resource using a semaphore that maintains separate access-request queues for different cores and uses a selectable scheduling algorithm to grant pending requests, one at a time. The semaphore signals the core whose request is granted by sending it an interrupt signal using a dedicated core line that is not part of the system bus. The granted request is then de-queued, and the core accesses the shared resource in response to receiving the interrupt signal. The use of dedicated core lines for transmitting interrupt signals from the semaphore to the cores alleviates the need for repeated polling of the semaphore on the system bus. The use of the scheduling algorithm prevents a potential race condition between contending cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.