PCIe switch with data and control path systolic array
US10261936B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Apr 24, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Apr 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present subject disclosure provides a PCIe switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.