Patent · US Active

Field programmable gate array bitstream verification

US10262098B1 · kind B1 · utility

1Cited by
4References
16Claims
0Family size

Assignee

Inventor

Key dates

Filing dateOct 29, 2015
Grant dateApr 16, 2019
Priority date—
Expiry dateAug 19, 2036

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2119/12
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Described herein are various technologies pertaining to confirming an integrity of a FPGA. A verifier circuit is placed into an FPGA bitstream to enable external verification of the FPGA configuration in real time without requiring readout of the FPGA configuration itself. Number generators are utilized to generate a key which is shared between the FPGA and an external verification component (VC). The key is utilized to configure an initial state of sequence registers respectively located on both the FPGA and the VC. When the FPGA is operating with an approved configuration, output from the sequence registers at the FPGA and the VC are the same.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.