Selective bit-line sensing method and storage device utilizing the same
US10262725B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Nov 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A selective bit-line sensing method is provided. The selective bit-line sensing method includes the steps of: generating a neuron weights information, the neuron weights information defines a distribution of 0's and 1's storing in the plurality of memory cells of the memory array; and selectively determining either the plurality of bit-lines or the plurality of complementary bit-lines to be sensed in a sensing operation according to the neuron weights information. When the plurality of bit-lines are determined to be sensed, the plurality of first word-lines are activated by the artificial neural network system through the selective bit-line detection circuit, and when the plurality of complementary bit-lines are determined to be sensed, the plurality of second word-lines are activated by the artificial neural network system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.