Method and apparatus for identifying erroneous data in at least one memory element
US10262752B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Dec 16, 2014 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Feb 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for identifying erroneous data in at least one memory element, particularly a register, that includes at least one flip-flop that is intended to allow reliable detection of soft errors. To this end, writing of data to the at least one memory element involves at least one write security bit being produced from these data and stored in an associated security memory element, wherein at least one output security bit is computed from the data continuously in the same way as for writing and is compared with the corresponding write security bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.