Memory device and method of disposing conduction lines of the same
US10262935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Aug 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.