Semiconductor memory devices
US10263006B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Apr 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/514
Abstract
A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.