Semiconductor device having vertical hall element
US10263176B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Dec 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
Abstract
A vertical Hall element having an improved sensitivity and reduced offset voltage includes: a second conductivity type semiconductor layer formed on a semiconductor substrate and having an impurity concentration that is distributed uniformly; a second conductivity type impurity diffusion layer formed on the semiconductor layer and having a concentration higher than in the semiconductor layer; a plurality of electrodes formed in a straight line on a surface of the impurity diffusion layer, and each formed from a second conductivity type impurity region that is higher in concentration than the impurity diffusion layer; and a plurality of first conductivity type electrode isolation diffusion layers each formed between two electrodes out of the plurality of electrodes on the surface of the impurity diffusion layer, to isolate the plurality of electrodes from one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.