Transient voltage suppressing integrated circuit
US10263417B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 2016 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Apr 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A transient voltage suppressing (TVS) integrated circuit includes an input output pin, a ground pin, a substrate, a first TVS die and a second TVS die. The substrate provides a common bus. The first TVS die is disposed on the substrate, and includes a first input output terminal and a first reference ground terminal. The second TVS die is disposed on the substrate and includes a second input output terminal and a second reference ground terminal. The second reference ground terminal is electrically coupled to the first reference ground terminal through the common bus, and the first input output terminal is coupled to the first input out pin, and the second input output terminal is coupled to a ground pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.