Circuit arrangement and method for gate-controlled power semiconductor devices
US10263506B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2016 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Jan 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/08148
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switch module includes a collector connection, an emitter connection, and a gate connection. The switch module includes a plurality of parallel connected switching elements, e.g., insulated-gate bipolar transistors, each having a collector electrode electrically connected to the collector connection, an emitter electrode electrically connected to the emitter connection, and a gate electrode electrically connected to the gate connection. A fault protection device is operatively electrically connected between the gate connection and the switching elements and comprises passive electrical components which are selected such that in the event of a fault in at least one of the plurality of switching elements, a gate-emitter voltage is provided to the gate electrodes of non-faulty switching elements in a passive manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.