Method and device for voltage balancing of DC bus capacitors of neutral-point clamped four-level inverter
US10263535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2018 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | May 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/5395
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method and a device for voltage balancing of DC bus capacitors of an NPC four-level inverter are disclosed. The method includes: determining an optimal zero-sequence voltage, determining an actual reference voltage of each phase based on the optimal zero-sequence voltage; comparing respectively three preset carrier signals with the actual reference voltage of each phase to obtain three first control signals; determining three duty-cycle adjustment values based on a voltage of the intermediate bus capacitor; adjusting correspondingly the three first control signals based the three duty-cycle adjustment values to obtain three second control signals; inputting correspondingly the three second control signals to three first switches of an upper bridge corresponding to each phase; and inputting correspondingly complementary signals of the three second control signals to three second switches of a lower bridge corresponding to each phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.