Physical layer circuitry for multi-wire interface
US10263762B2 · kind B2 · utility
1Cited by
1References
18Claims
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Key dates
| Filing date | Jul 19, 2018 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Jul 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M1/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.