Protected container key management processors, methods, systems, and instructions
US10263988B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2016 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Dec 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A processor of an aspect includes a decode unit to decode an instruction. The instruction to indicate a first structure in a protected container memory and to indicate a second structure in the protected container memory. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine whether a status indicator is configured to allow at least one key to be exchanged between the first and second structures, and is to exchange the at least one key between the first and second structures when the status indicator is configured to allow the at least one key to be exchanged between the first and second structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.