Reconfigurable test access port with finite state machine control
US10267850B2 · kind B2 · utility
2Cited by
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20Claims
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Key dates
| Filing date | Dec 22, 2014 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Dec 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes logic to implement a reconfigurable test access port with finite state machine control. A plurality of test access ports may each include a finite state machine for enabling implementation of different test interfaces to the processor, including JTAG IEEE 1149.1, JTAG IEEE 1149.7, and serial wire debug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.