Processor memory architecture
US10268382B2 · kind B2 · utility
2Cited by
1References
26Claims
0Family size
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Key dates
| Filing date | Jan 28, 2016 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Mar 15, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device includes a first memory interface for accessing a first memory device of a main memory. Each first memory interface is compatible with Low-Power Double-Data-Rate (LPDDR) signaling. The processing device further includes a second memory interface, which has different signaling characteristics from the first memory interface, for accessing a second memory device of the main memory. The second memory device has an access latency higher than the first memory device and lower than a secondary storage device. The first memory device and the second memory device may be used as a dual memory or a two-tiered memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.