Flexible array substrate with stress relief layer openings
US10269829B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 24, 2017 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Jan 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
Abstract
An array substrate and a flexible display panel are provided. The array substrate includes a flexible substrate, a thin film transistor, a first metal layer, a second metal layer and a stacked structure including multiple inorganic layers. The thin film transistor includes a source, a drain, a channel and a gate. The gate of the thin film transistor is insulated from the source, the channel and the drain. The multiple inorganic layers include one or more buffer layers between the flexible substrate and the thin film transistor, one or more gate insulating layers between a channel area and the gate, and a first isolating layer between the thin film transistor and the second metal layer. At least one inorganic layer of the multiple inorganic layers has multiple openings at a position corresponding to a display area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.