Semiconductor device layout and method for forming same
US10269951B2 · kind B2 · utility
0Cited by
6References
5Claims
0Family size
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Key dates
| Filing date | May 16, 2017 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Jun 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
Abstract
A semiconductor device is provided. The semiconductor device includes a semiconductor device layer having silicon carbide and having an upper surface and a lower surface. The semiconductor device also includes a heavily doped body region formed in the upper surface of the semiconductor device layer. The semiconductor device further includes a gate stack formed adjacent to and on top of the upper surface of the semiconductor device layer, wherein the gate stack is not formed adjacent to the heavily doped body region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.