Buffer circuit
US10270446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2017 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | May 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017536
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer circuit receives a working supply voltage which may vary within a voltage range. The buffer circuit has a high voltage constant current buffer circuit, and in this circuit, the source of the first NMOS transistor is grounded, and drains of the first NMOS transistor and the first PMOS transistor are connected. The source of the second PMOS transistor is connected to the supply voltage input of the buffer circuit, and the drain of the second PMOS transistor is connected to the source of the first PMOS transistor. The input end of the high voltage diode connected composite transistors is connected to the supply voltage input of the buffer circuit, and the output end of the diode connected transistors is connected to the gates of first and second PMOS transistors. The first PMOS and NMOS transistors are high-voltage transistors. The second PMOS transistor is a low-voltage transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.