Coarse delay lock estimation for digital DLL circuits
US10270453B2 · kind B2 · utility
8Cited by
3References
19Claims
0Family size
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Key dates
| Filing date | Apr 2, 2016 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Nov 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.