Interruptible and restartable matrix multiplication instructions, processors, methods, and systems
US10275243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2016 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Nov 5, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3865
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.