Detection of error patterns in memory dies
US10275307B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2017 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Mar 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided. In an example, the method includes identifying a memory module that includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a plurality of memory regions, and each memory die of the plurality of memory dies services a respective portion of a data access. An error pattern is detected in a first memory region of the plurality of memory regions. The first memory region is associated with a first memory die of the plurality of memory dies. Based on the detected error pattern, the first memory region of the first memory die is marked as erased without marking a second memory region of the first memory die as erased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.