Simultaneous inbound multi-packet processing
US10275388B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2016 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Jul 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes an input/output adapter operable to receive packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet on a first pipeline and a second packet on a second pipeline in a same clock cycle. The controller is further operable to route a header portion of the first packet and a header portion of the second packet on a header path to a header buffer including a plurality of physical arrays in parallel through a header buffer write interface having a single offset address. The controller is operable to route a payload portion of the first packet and a payload portion of the second packet on a data path to a data buffer including a plurality of physical arrays in parallel through a data buffer write interface having a single offset address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.