Gate driver with reduced number of thin film transistors and display device including the same
US10276121B2 · kind B2 · utility
5Cited by
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20Claims
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Key dates
| Filing date | Dec 14, 2016 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Feb 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/045
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a gate driver, a Q node is shared by two channels to output a scan signal at high level, and a QB node is shared by four channels to output a scan signal at low level. Accordingly, the number of thin-film transistors required to configure four channels of a gate-in-panel (GIP) is reduced, such that the bezel size can be reduced. Further, the gate driver includes a compensation capacitor or a discharge transistor disposed in some of the channels sharing the Q node, such that deviation in output characteristics among the channels sharing the Q node can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.