Fan-out semiconductor package
US10276467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2017 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Feb 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fan-out semiconductor package includes: a fan-out semiconductor package may include: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a reinforcing layer disposed on the encapsulant. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.