Array substrate and repairing method thereof
US10276603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2016 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Oct 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/00
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present application discloses an array substrate including a first signal line layer having a plurality of rows of first signal lines; a second signal line layer having a plurality of columns of second signal lines; the plurality of rows of first signal lines crossing over the plurality of columns of second signal lines defining a plurality of subpixels; a first insulating layer and a second insulating layer between the first signal line layer and the second signal line layer; the first insulating layer on a side of the second insulating layer proximal to the first signal line layer; a repair line between the first insulating layer and the second insulating layer, the repair line corresponding to one of the plurality of columns of second signal lines; and a first via and a second via extending through the second insulating layer; the repair line being electrically connected to the corresponding one of the plurality of columns of second signal lines through the first via and the second via, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.