Time-of-fight pixel including in-pixel buried channel transistors
US10276628B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2017 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Oct 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8057
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An imaging device, including a monolithic semiconductor integrated circuit substrate, comprises a focal plane array of pixel cells. Each one of the pixel cells includes a gate overlying a region of the substrate operable to convert incident radiation into charge carriers. The pixel also includes a CMOS readout circuit including at least one output transistor in the substrate. The pixel further includes a charge coupled device section on the substrate adjacent the gate, the charge coupled device section including a sense node to receive charge carriers transferred from the region of the substrate beneath the gate. The sense node is coupled to the output transistor. The pixel also includes a reset switch coupled to the sense node. The pixel's charge coupled device section has a buried channel region. The pixel also includes one or more bias enabling switches operable to enable a bias voltage to be applied to the gate. At least one of the reset switch or the one or more bias enabling switches is formed in the buried channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.