Semiconductor memory structure with magnetic tunnel junction (MTJ) cell
US10276634B2 · kind B2 · utility
2Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Jun 20, 2017 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Jun 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
Abstract
A semiconductor memory structure is provided. The semiconductor memory structure includes a bottom electrode formed over a substrate and a magnetic tunneling junction (MTJ) cell formed over the bottom electrode. The semiconductor memory structure includes a top electrode formed over the MTJ cell and a passivation layer surrounding the top electrode. The passivation layer has a recessed portion that is lower than a top surface of the top electrode. The semiconductor memory structure further includes a cap layer formed on the top electrode and the passivation layer, wherein the cap layer is formed in the recessed portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.