Integrated circuit device and method of manufacturing the same
US10276675B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2018 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Apr 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a source/drain region having a recess in its top, a contact plug extending on the source/drain region from within the recess, and a metal silicide layer lining the recess and having a first portion covering a bottom of the contact plug and a second portion that is integral with the first portion and covers a lower part of sides of the contact plug. The second portion of the silicide layer may have a thickness different from a thickness of the first portion of the silicide layer. The silicide layer is formed at a relatively low temperature to offer an improved resistance characteristic as between the source/drain region and the contact plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.