Scalable process for the formation of self aligned, planar electrodes for devices employing one or two dimensional lattice structures

US10276698B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Michael Engel · Karlsruhe, DE
• Mathias B. Steiner · Rio de Janeiro, BR

Key dates

• Filing date: Oct 21, 2015
• Grant date: Apr 30, 2019
• Expiry date: Oct 21, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10K85/221

Abstract

A method of forming an electrical device that includes forming a gate dielectric layer over a gate electrode, forming source and drain electrodes on opposing sides of the gate electrode, wherein one end of the source and drain electrodes provides a coplanar surface with the gate dielectric, and positioning a 1D or 2D nanoscale material on the coplanar surface to provide the channel region of the electrical device.