Transistor with asymmetric source and drain regions
US10276716B2 · kind B2 · utility
1Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Nov 2, 2016 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Nov 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/661
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.