Architecture to scale finite-state machines across integrated circuits using a digital bus
US10277068B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Feb 9, 2017 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Jun 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02J1/102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprises a plurality of power supplies, wherein a power supply provides a supply voltage rail to a voltage domain of the system; a plurality of power supply voltage sequencer devices electrically coupled to multiple power supplies of the plurality of power supplies, wherein a voltage sequencer device is configured to activate the multiple power supplies in a specified sequence; and a bus electrically coupled to the plurality of power supply voltage sequencer devices, wherein the bus is configured to communicate state information of the plurality of power supply voltage sequencer devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.