Method to improve latency in an ethernet PHY device
US10277433B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2017 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Nov 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/0014
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to data communication networks. An example data communication apparatus includes physical (PHY) layer circuitry that includes transceiver circuitry, decoder circuitry, and a signal analysis unit. The transceiver circuitry receives encoded data symbols via a network link. The received encoded data symbols are encoded using trellis coded modulation (TCM). The decoder circuitry decodes the received encoded data symbols using maximum-likelihood (ML) decoding to map a received symbol sequence to an allowed symbol sequence using a trace-back depth. A trace-back depth value is a number of symbols in the received symbol sequence used by the ML decoding to identify the allowed symbol sequence from the received symbol sequence. The signal analysis unit determines one or more link statistics of the network link, and sets the trace-back depth value according to the one or more link statistics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.