Memory interface circuitry with distributed data reordering capabilities
US10282109B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 15, 2016 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Nov 9, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit may include memory interface circuitry for communicating with an external or in-package memory module. The integrated circuit may also include out-of-order (OOO) clients and in-order (IO) clients that issue read and write commands to the memory interface circuitry. The memory interface circuitry may include a memory controller having an OOO command scheduler, a write data buffer, and a simple read data pipeline. The memory interface circuitry may also include a multiport arbitration circuit for interfacing with the multiple clients and also OOO adaptor circuits interposed between the multiport arbitration circuit and the IO clients. Each of the OOO adaptor circuits may include an ID generator and a local reordering buffer and may allow the memory controller to return data to the various clients without throttling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.