Adaptive wear levelling
US10282111B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2016 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Jun 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device that provides for adaptive wear levelling includes at least one processor. The at least one processor utilizes sets of blocks of flash memory circuits for data storage operations, each set of blocks including a block from each flash memory circuit and at least some of the blocks being marked active for the data storage operations. The at least one processor monitors a quality metric of each block while the blocks marked active are utilized for data storage operations. The at least one processor determines when the quality metric of a block falls below a minimum level and marks the block as temporarily inactive, where the block is not utilized for the data storage operations while marked temporarily inactive. The at least one processor, when a criterion is satisfied, marks the block as active so that the block can again be utilized for the data storage operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.