Alias register file for supporting mixed width datapath in a configurable processor
US10282206B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Jun 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30112
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to certain general aspects, the present embodiments allow register files and states with different data types to share logic area while minimizing unnecessary use of power in a configurable processor. Embodiments include allowing configurable processor designers to describe alias register files and states. Using alias register files and states, designers can implement vector and scalar operations on different register files, but the scalar register file can be implemented on the vector register file. In addition, the upper lanes of the vector register file can be clock gated when the scalar operation performs computations. With this gating, the clocks for the entire upper lanes (including the register file, state, semantic, mux, decoder) can be disabled, which provides power savings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.