Zeroing a cache line

US10282296B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jason W. Brandt · Austin, US
• Robert S. Chappell · Portland, US
• Jesus Corbal · King City, US
• Edward T. Grochowski · San Jose, US
• Stephen H. Gunther · Beaverton, US
• Buford M. Guy · Austin, US
• Thomas R. Huff · Portland, US
• Elmoustapha Ould-Ahmed-Vall · Chandler, US
• Bret L. Toll · Hillsboro, US
• David B. Papworth · Beaverton, US
• James D. Allen, IV · Broomfield, US

Key dates

• Filing date: Dec 12, 2016
• Grant date: May 7, 2019
• Expiry date: Dec 12, 2036

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.