Patent · US Active

Three-stage memory arrangement

US10282320B2 · kind B2 · utility

0Cited by

2References

14Claims

0Family size

Assignee

Continental Teves AG & Co. OHG · DE

Inventors

Joern Schriefer · Griesheim, DE
Juergen Scherschmidt · Frankfurt, DE
Thomas Peichl · Mellrichstadt, DE

Key dates

Filing date	Jul 22, 2011
Grant date	May 7, 2019
Priority date	—
Expiry date	Apr 21, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG05B19/042
WIPO fieldControl
WIPO sectorInstruments

Abstract

An electronic memory arrangement having at least three memory areas, a memory control unit, and a writing memory-accessing unit configured to carry out write access. A reading memory-accessing unit is configured to carry out read accesses. The memory control unit determines read and write access to the at least three memory areas, and the memory control unit is configured such that after the writing of a first data packet to one of the three memory areas, a following second data packet to be written is written to one on the three memory area to which read access does not place simultaneously during the write access of the second data packet.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.