Flexible constraint integrated circuit implementation runs
US10282502B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Mar 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are provided for automatically performing multiple integrated circuit implementation runs with variations of input design constraints. Input design constraints can be automatically adjusted to create multiple modified versions of the design constraints. The multiple modified design constraints can be used to perform separate integrated circuit implementation runs for a given circuit design. Results of the multiple implementation runs can be analyzed, and a circuit implementation report can be generated based on the results of the runs performed with the various modified design constraints. In some embodiments, a circuit implementation recommendation can be generated based on the implementation run results. In at least some scenarios, the multiple implementation runs can be performed using multiple synthesis and implementation processes. The multiple synthesis and implementation processes can be distributed across one or more host computing devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.