Device for implementing artificial neural network with multiple instruction units
US10282659B2 · kind B2 · utility
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3References
12Claims
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Assignee
Inventors
Key dates
| Filing date | May 22, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | May 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, a first instruction unit, a second instruction unit, an instruction distributing unit, a data transferring controller, a buffer module and a computation module. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.