Digital architecture with merged non-linear emission clock signals for a display panel
US10283037B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2016 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | May 19, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0285
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Systems and apparatuses provide a digital architecture with merged non-linear emission clocks for a display panel. In one embodiment, a display driver hardware circuit includes decoder logic to store a mapping between a plurality of non-linear gray scale clock signals and a merged non-linear gray scale clock signal that represents a combination of the plurality of non-linear gray scale clock signals including first and second non-linear gray scale clock signals. In one example, the first non-linear gray scale clock signal is associated with at least one display element of a first color and the second non-linear gray scale clock signal is associated with at least one display element of a second color. A driver circuitry is coupled to the decoder logic. The driver circuitry includes a counter to store a number of pulses of the merged non-linear gray scale clock signal and driving circuitry to cause emission of the at least one display element of a first color based on the first non-linear gray scale clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.