Display with cell voltage compensation
US10283053B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Apr 5, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An active matrix display wherein each cell comprises: two thin-film transistors (TFTs) connected in series, the first TFT having its drain connected to a high supply line and the second TFT having its source connected to a low supply line. Gates of the first and second TFTs are selectively connected to respective first and second data driver signals under the control of a scan line signal. A storage capacitance is connected to a node joining the first and second TFT. A driving TFT has a gate connected to the joining node and is connected to drive a light emitting device with a bias current. In one embodiment, the first and second TFTs are sized relative to one another and the first and second data driver signal voltages are related proportionally, so that the data driver signals and the bias current are related to one another by a function substantially independent of a threshold voltage of the driving TFT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.