Method and system for controller hold-margin of semiconductor memory device
US10283177B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2018 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Aug 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for controlling a hold-margin in a semiconductor memory device includes a programmable RC network communicatively coupled to a delay logic circuit, a latch clock generator and a latch circuit. A delay associated with a clock path is induced using a combination of a logic circuit and a wire placed across at least one of a column and a row of the semiconductor memory device. A delay associated with the data path is induced using a combination of the delay logic circuit and at least one of the load cell and a wire routed across at least one of a column and a row of the semiconductor memory device. The system controls the hold-margin based on the delay associated with the data path and the delay associated with the clock path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.