Time tracking circuit for FRAM
US10283181B2 · kind B2 · utility
4Cited by
2References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 1, 2016 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Aug 17, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/2293
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit includes a controller to output a signal to an input of a driver; a transistor coupled an output of the driver; the driver to, in response to receiving the signal, output a first voltage to the transistor; and the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.